(China (Mainland))
Product Summary
The ISPLSI1016EA-125LJ is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, one Dedicated Input pin, two Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The ISPLSI1016EA-125LJ provides complete interconnectivity between all of these elements. The ISPLSI1016EA-125LJ features 5V in-system programmability (ISP™) and in-system diagnostic capabilities via an IEEE 1149.1 Test Access Port. The device offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ISPLSI1016EA-125LJ architecture, the device adds user-selectable 3.3V or 5V I/O and open-drain output options.
Parametrics
ISPLSI1016EA-125LJ absolute maximum ratings: (1)Supply Voltage VCC: -0.5 to +7.0V; (2)Input Voltage Applied: -2.5 to VCC +1.0V; (3)Off-State Output Voltage Applied: -2.5 to VCC +1.0V; (4)Storage Temperature: -65 to 150℃; (5)Case Temp. with Power Applied:. -55 to 125℃; (6)Max. Junction Temp. (TJ) with Power Applied: 150℃.
Features
ISPLSI1016EA-125LJ features: 1)2000 PLD Gates; (2)32 I/O Pins, One Dedicated Input; (3)96 Registers; (4)High-Speed Global Interconnect; (5)Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc; (6)Small Logic Block Size for Random Logic; (7)Functionally Compatible with ispLSI 1016E; (8)fmax = 200 MHz Maximum Operating Frequency; (9)tpd = 4.5 ns Propagation Delay; (10)TTL Compatible Inputs and Outputs; (11)Electrically Erasable and Reprogrammable; (12)Non-Volatile; (13)100% Tested at Time of Manufacture; (14)Unused Product Term Shutdown Saves Power.
Diagrams
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ispLSI 1016-110LJ |
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ispLSI 1016-60LJ |
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ispLSI 1016-60LJI |
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CPLD - Complex Programmable Logic Devices USE ispMACH 4000V |
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ispLSI 1016-60LT44 |
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CPLD - Complex Programmable Logic Devices USE ispMACH 4000V |
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