(China (Mainland))
Product Summary
The XC18V01PCG20C is an in-system programmable configuration PROM. The XC18V01PCG20C can be cascaded by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. The XC18V01PCG20C is compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable serial PROM family.When the FPGA is in Master Serial mode, the XC18V01PCG20C generates a configuration clock that drives the PROM. A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.
Parametrics
XC18V01PCG20C absolute maximum ratings: (1)VCCINT/VCCO, Supply voltage relative to GND: –0.5 to +4.0 V; (2)VIN, Input voltage with respect to GND: –0.5 to +5.5 V; (3)VTS, Voltage applied to high-Z output: –0.5 to +5.5 V; (4)TSTG, Storage temperature (ambient): –65 to +150℃; (5)TJ, Junction temperature: +125℃.
Features
XC18V01PCG20C features: (1)In-System Programmable 3.3V PROMs for; (2)Configuration of Xilinx FPGAs: Endurance of 20,000 Program/Erase Cycles; Program/Erase Over Full Industrial Voltage and Temperature Range (-40 to +85℃); (3)IEEE Std 1149.1 Boundary-Scan (JTAG) Support; (4)JTAG Command Initiation of Standard FPGA Configuration; (5)Simple Interface to the FPGA; (6)Cascadable for Storing Longer or Multiple Bitstreams; (7)Low-Power Advanced CMOS FLASH Process; (8)Dual Configuration Modes: Serial Slow/Fast Configuration (up to 33 MHz); Parallel (up to 264 Mb/s at 33 MHz); (9)5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals; (10)3.3V or 2.5V Output Capability; (11)Lead-Free (Pb-Free) Packaging.
Diagrams
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XC18V04VQG44C |
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XC18V02VQG44C |
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XC18V02 |
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XC18V00 |
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XC1800 |
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Negotiable |
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