HD6412350F20V

microcomputer, QFP, -0.3 to +7.0V

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Price:: US $2.60~3.30 / piece [Get Latest Price]

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	US $2.60~3.30

PartNumber:: HD6412350F20V

Brand:: Renesas Technology Corp - Renesas | Pack: QFP | D/C: 08+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-12-08

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Part Number:HD6412350F20V
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Product Summary

The HD6412350F20V is a microcomputer. It is equipped with peripheral functions on-chip. The HD6412350F20V CPU has an internal 32-bit architecture. It is provided with sixteen 16-bit general registers and a concise. The HD6412350F20V is designed for high-speed operation, and can address a 16-Mbyte linear address space. It has on-chip mask ROM. The HD6412350F20V supports three operating modes (modes 1, 4, and 5). There is a choice of address space and single-chip mode or expansion mode.

Parametrics

HD6412350F20V absolute maximum ratings: (1)Power supply voltage VCC: -0.3 to +7.0 V; (2)Input voltage (except port 4) Vin: -0.3 to VCC +0.3 V; (3)Input voltage (port 4) Vin: -0.3 to AVCC +0.3 V; (4)Reference voltage Vref: -0.3 to AVCC +0.3 V; (5)Analog power supply voltage AVCC: -0.3 to +7.0 V; (6)Analog input voltage VAN: -0.3 to AVCC +0.3 V; (7)Operating temperature Topr, Regular specifications: -20 to +75℃; Wide-range specifications: 40 to +85℃; (8)Storage temperature Tstg: -55 to +125℃.

Features

HD6412350F20V features: (1)General-register machine; (2)Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers); (3)High-speed operation suitable for realtime control; (4)Maximum clock rate: 20 MHz; (5)High-speed arithmetic operations; (6)Instruction set suitable for high-speed operation; (7)Sixty-five basic instructions; (8)8/16/32-bit move/arithmetic and logic instructions; (9)Unsigned/signed multiply and divide instructions; (10)Powerful bit-manipulation instructions; (11)Two CPU operating modes; (12)Normal mode : 64-kbyte address space; (13)Advanced mode : 16-Mbyte address space; (14)Chip select output possible for each area; (15)Choice of 8-bit or 16-bit access space for each area.