IS42S16800B-7TLI

Product Summary

The IS42S16800B-7TLI is a 128-mbit synchronous dram. ISSI 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows. The IS42S16800B-7TLI is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V VDD and 3.3V VDDQ memory systems containing 134,217,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows by 512 columns by 16 bits or 4,096 rows by 1,024 columns by 8 bits. The IS42S16800B-7TLI includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.

Parametrics

IS42S16800B-7TLI absolute maximum ratings: (1)VDD MAX Maximum Supply Voltage: –0.5 to +4.6 V; (2)VDDQ; (3)MAX Maximum Supply Voltage for Output Buffer: –0.5 to +4.6 V; (4)VIN Input Voltage: –0.5 to VDD + 0.5 V; (5)VOUT Output Voltage: –1.0 to VDDQ + 0.5 V; (6)PD MAX Allowable Power Dissipation: 1 W; (7)ICS Output Shorted Current: 50 mA; (8)TOPR Operating Temperature Com: 0 to +70 ℃ Ind. –40 to +85; (9)TSTG Storage Temperature: –65 to +150 ℃.

Features

IS42S16800B-7TLI features: (1)Clock frequency: 167, 143, 133 MHz; (2)Fully synchronous; all signals referenced to a positive clock edge; (3)Internal bank for hiding row access/precharge; (4)LVTTL interface; (5)Programmable burst length(1, 2, 4, 8, full page); (6)Programmable burst sequence: Sequential/Interleave; (7)Auto Refresh (CBR); (8)Self Refresh with programmable refresh periods; (9)4096 refresh cycles every 64 ms; (10)Random column address every clock cycle; (11)Programmable CAS latency (2, 3 clocks); (12)Burst read/write and burst read/single write operations capability; (13)Burst termination by burst stop and precharge command; (14)Industrial Temperature Availability; (15)Lead-free Availability.

Diagrams